BLT - The FPGA Experts

Yesterday, our Technical Director co-presented an AMD SDR Reference Design at the AMD Signal Processing Working Group in Longmont, CO and tonight we're putting it on display. This solution, built on AMD Versal™ adaptive SoCs, eliminates DSP bottlenecks and accelerates software-defined radio development at the tactical edge.

If you're at AMD Partner Night, stop by our table for a live demo. Come see it in action! 🔊📡

Will you be at any of these events? Be sure to catch up with our BLT team.

Is your FPGA design having timing issues? Timing issues are often tied to utilization. The Vivado Utilization Report helps identify where the problem is. In our latest blog post we'll break it down. READ: https://bltinc.com/2026/04/22/understanding-the-vivado-utilization-report/