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Analysis and construction
of sequence networks
Basic course level
Preparation tasks (must be done BEFORE the lab starts):
The schematic below is drawn in a different program than ORCAD, which works so that NAND gates are drawn
with a triangle on the output instead of a circle (so all the gates in the schematic are two- or three-input NAND)
and flip-flops are drawn with common clocks - respectively travel inputs. The scheme thus contains four flipflops, three of which are connected, and on reset all are reset and on a positive edge on CLK all are updated.
The feedback wires are not drawn either, but it is assumed that, for example, Q2' in the left part of the diagram
is connected to Q2' in the right part, etc.
Draw a table of all states with Q2Q1Q0 as input signals and Q2+Q1+Q0+as output signals.
Then draw state diagrams.
The design is supposed to work like a dice (so count 1, 2, 3, 4, 5, 6, 1, 2, …), but contains a serious error,
which in a PLD with automatic Power-on-reset (so where all flip-flops are reset to zero at start-up) would
cause a malfunction immediately. Explain why!
Answer…………………………………………………………………………………………………………………………………………
……………………………………………………
You will now construct a state machine in the form of a two-bit counter that counts in the sequence 0
– 1 – 2 – 3. When we get to state 3, the counter must stay there until we activate "Reset" and then it
starts over from 0 again .
The counter must have a "Hold signal" that works so that when Hold = '1' the counter is locked in its
current position, but if Hold = '0' it goes to the next position when a clock pulse arrives (except in state
3, that is) .
The calculator must also have an output signal U which shows that we have started counting. It must therefore
be '1' in all states except the start state.
Draw the state diagram for this machine. The diagram must contain states ("bubbles"), the input signal H and
the output signal U. The reset signal does not need to be included in the state diagram, it can be connected
directly to the reset inputs of the D flip-flops.
Derive logical expressions for the D-inputs of the flip-flops and the output signal.
Draw the schematic of the machine in ORCAD with D flip-flops and optional logic gates (OR gates must
have two inputs though).
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